1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to an MOS semiconductor device having an interface between a semiconductor layer and an insulating layer, wherein the interface has a reduced interface state, and the MOS semiconductor device has suppressed variation of performances and reduced leakage of current.
Priority is claimed on Japanese Patent Application No. 2007-102493, filed Apr. 10, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
The MOS (Metal Oxide Semiconductor) semiconductor device includes a semiconductor substrate which has a device region which is defined and isolated by an insulating film. The insulating film has an interface with the semiconductor substrate or device region. The interface between semiconductor and insulator has an interface state that is caused by dangling bonds of semiconductor and lattice defects of semiconductor. The interface state performs as traps to carriers. The interface state may cause generation current and increase leakage of current unless the interface state is sufficiently reduced to suppress such generation current and leakage of current.
The MOS (Metal Oxide Semiconductor) semiconductor device also includes a gate insulating film which has an interface with the semiconductor substrate. The interface between the semiconductor substrate and the gate insulating film also has an interface state. The interface state may cause variation of threshold voltage over time and deteriorate the reliability of the semiconductor device.
In a memory cell of a dynamic random access memory (DRAM), increase of leakage of current or variation of threshold voltage may deteriorate refresh performance.
A conventional method for reducing interface state has been known, wherein a heat treatment is carried out in hydrogen atmosphere to terminate dangling bonds of silicon with hydrogen, thereby forming Si—H bonds at the terminals.
Si—H bonds are likely to be broken by thermal stress application and hot carrier injection, thereby generating dangling bonds. Another conventional method was proposed in order to prevent this phenomenon. In accordance with the other conventional method, fluorine is introduced into a silicon-insulator interface to form Si—F bonds which are higher in bonding force than Si—H bonds.
There are several methods of introducing fluorine. An ion-implantation is most convenient.
Japanese Unexamined Patent Application, First Publication, No. 2000-269492 discloses that after source and drain regions are formed, fluorine is ion-implanted into the entire surface of a silicon substrate and then a heat treatment is carried out, thereby terminating dangling bonds with fluorine.
Japanese Unexamined Patent Application, First Publication, No. 5-251463 discloses that after an LDD (Lightly Doped Drain) is formed by an ion-implantation and before side walls are formed, a silicon substrate is lamp-annealed in an atmosphere containing fluorine compounds, thereby introducing fluorine into a gate insulating film.
Japanese Unexamined Patent Application, First Publication, No. 2005-032864 discloses that at the same time of forming LDD or source/drain regions, fluorine or fluorine-compound is introduced into a gate electrode over a thicker gate insulating film.
Direct implantation of fluorine into a silicon substrate may generate a large number of point defects in the silicon substrate. Sufficient recovery of a large number of point defects needs high temperature heat treatment. Such high temperature heat treatment makes it difficult to realize the shrinkage of a semiconductor device. In practice, suppressing process temperature is needed for an advanced semiconductor device. Low temperature heat treatment that is suitable for realizing the shrinkage of a semiconductor device may cause insufficient recovery, thereby allowing point defects to reside in a depletion layer. Such residual point defects may cause junction leakage, thereby deteriorating the performance of a semiconductor device.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and/or a method of forming a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.